1. Field of the Invention
This invention relates generally to random access memory, and more particularly to write leveling delay determination for memory interfaces.
2. Description of the Related Art
Double data rate (DDR) synchronous dynamic random access memory (SDRAM) is a class of memory capable of providing approximately twice the bandwidth of single data rate SDRAM. DDR SDRAM achieves this increased bandwidth without requiring an increased clock frequency by transferring data on both the rising and falling edges of the clock signal. Because the increased bandwidth, DDR SDRAM often is used in the design of integrated circuits.
DDR SDRAM integrated circuits often are used in dual in-line memory modules (DIMMs) for use in a computer system. A typical DIMM includes a plurality of DDR SDRAM integrated circuits mounted on a printed circuit board for use in a personal computer system, workstation, or server. DIMMs include inputs for clock and command signals as well as input/ouput (I/O) interfaces for data, both of which are designed to work together to write and read data from the individual DDR SDRAM integrated circuits.
FIG. 1 is a block diagram showing a prior art DDR DIMM 100 architecture using DDR SDRAM integrated circuit devices. As illustrated in FIG. 1, the DDR DIMM 100 includes a plurality of DDR memory devices 102a-102h disposed on a printed circuit board 104. Coupled to each DDR memory device 102a-102h is a set of data/data strobe signal (DQS) lines 106. Each set of data/DQS lines 106 provide I/O for each DDR memory devices 102a-102h. As will be appreciated by those skilled in the art, DDR memory devices require separate control lines that are unique to each memory device and distributed in parallel. These parallel control lines are known as data strobe signal (DQS) lines and are generated from a differential clock fed to each DDR memory device 102a-102h and a DLL located within each DDR memory device 102a-102h. The DQS signal allows each DDR memory device 102a-102h to launch data from the memory device at the same instant as a data-valid signal is needed. Also included in the DDR DIMM 100 are clock and command signal lines 108, which provide clock and command signals to each of the DDR memory devices 102a-102h. 
As illustrated in FIG. 1, the clock and command signal lines 108 are connected to each DDR memory device 102a-102h on the DDR DIMM 100 in a parallel configuration. That is, the clock and command signal lines 108 are provided to each DDR memory device 102a-102h simultaneously. In this manner, each DDR memory device 102a-102h provides or receives data to/from its associated data/DQS lines 106 at approximately the same time. For example, in FIG. 1 each DDR memory device 102a-102h provides eight bits of a 64 byte read request in response to receiving a read command on the clock and command lines 108 at approximately the same time, allowing a memory controller to fetch 64 bits of data using a single read command.
However, with increased user needs in the form of speed and performance, more advanced memory circuits have been developed. One such advance is double data rate three (DDR3) SDRAM. DDR3 SDRAM is an improvement over DDR SDRAM that allows input/output (I/O) transfer at about eight times the speed of the memory cells contained in the DDR SDRAM. Moreover, DDR3 requires less power to operate than normal DDR SDRAM. However, to accommodate the newer DDR3 SDRAM integrated circuits, a new DIMM architecture was developed that changes the manner in which off-board clock and command signals are provided to the individual DDR3 SDRAM integrated circuits located on the DIMM, as illustrated next with reference to FIG. 2.
FIG. 2 is a block diagram showing a prior art DDR3 DIMM 200 architecture using DDR3 SDRAM integrated circuit devices. As illustrated in FIG. 2, the DDR3 DIMM 200 includes a plurality of DDR3 memory devices 202a-202h disposed on a printed circuit board 204. Coupled to each DDR3 memory device 202a-202h is a set of data/DQS lines 206, which provide I/O for each DDR3 memory devices 202a-202h. Also included in the DDR3 DIMM 200 are clock and command signal lines 208, which provide clock and command signals to each of the DDR3 memory devices 202a-202h. 
However, unlike the DDR DIMM 100 illustrated in FIG. 1, the DDR3 DIMM 200 is configured in a fly-by topology in which the clock and command signal lines 208 are connected in series to each DDR3 memory device 202a-202h on the DDR3 DIMM 200 in a daisy chain configuration. That is, the clock and command signal lines 208 are first provided to DDR3 memory device 202a, then to DDR3 memory device 202b, then to DDR3 memory device 202c, and so on to DDR3 memory device 202h. Consequently, DDR3 memory device 202a receives and acts on the received clock and command signals prior to DDR3 memory device 202b. Similarly, DDR3 memory device 202b receives and acts on the received clock and command signals prior to DDR3 memory device 202c, and so on until DDR3 memory device 202h receives and acts on the received clock and command signals last after DDR3 memory devices 202a-202h. This configuration reduces the number of stubs and the stub lengths, and allows termination to be placed just at the end of the clock and command signals. As a result, this design improves signal characteristics over the DDR DIMM 100 illustrated in FIG. 1.
However, as illustrated in FIG. 2, the data/DQS lines 206 are not configured in a daisy chain configuration. Hence, when a write command is provided to the DDR3 DIMM 200, each DDR3 memory device 202a-202h will see the command at a slightly different time, and as a result, will need to receive data on the data/DQS lines 206 at a slightly different time in order to align the data with the command on the DDR3 DIMM 200. Similarly, when a read command is provided to the DDR3 DIMM 200, each DDR3 memory device 202a-202h will provide the requested read data on its data/DQS lines 206 at a slightly different time.
In view of the foregoing, there is a need for systems and methods for determining proper delays to allow alignment between commands and data in a DDR3 memory interface. The methods should allow for automatic determination of the proper delay times, thus allowing a DDR3 DIMM to be properly integrated into a larger system.